1. Field of the Invention
This invention relates generally to logic circuits. In particularly, the invention relates to a method for reducing the transistor count in differential cascode voltage switch logic.
2. Background Art
A logic technology that has been gaining widespread acceptance is differential cascode voltage switch (DCVS) logic. Single-ended cascode voltage switches have been described by Hiltebeitel in a technical article "CMOS XOR" in the IBM Technical Disclosure Bulletin, Vol. 24, No. 11A, April 1982 at pages 5470 and 5471. Double-ended or differential cascode voltage switch logic will be described in more detail here but has previously been described by Carter, et at. in a technical article entitled "Cascode Parity Circuit", appearing in the IBM Technical Disclosure Bulletin, Vol. 24, number 3, August 1981 at pages 1705 and 1706.
The principles of operation of DCVS will be briefly described with reference to FIG. 1. In DCVS, two loads 10 and 12 are connected to a power supply line 13 at a fixed positive voltage V.sub.H and the other ends of the loads 10 and 12 are respectively connected to a complemented output line 14 and a true output line 16. Typically, the loads 10 and 12 are PMOS transistors having their gates cross-coupled to the drains of the other transistors. However, resistive or depletion NMOS loads are also used. A complemented output signal V.sub.OUT on the complemented output line 14 is the complement of a true output signal V.sub.OUT on the true output line 16. The true and complemented output lines 16 and 14 are connected through a logic block 18 to ground. Internal to the logic block 18 is a tree-like structure of field-effect transistors (FETs), which are controlled by one or more pairs of true and complemented input signals V.sub.1, V.sub.1 . . . V.sub.N, V.sub.N. The FETs are usually of the NMOS type with the PMOS load devices just described. The logic tree is arranged such that any combination of the controlling signals produces one and only one conduction path through the logic block 18. This conduction path connects either the true output line 16 or the complemented output line 14 to ground. The output line 14 or 16 having a conduction path through the logic 18 to ground is at the ground potential while the other output line 16 or 14 is at the power supply voltage V.sub.H.
It is typical that there be multiple stages of the DCVS circuit of FIG. 1 such that the outputs of one stage provide at least a portion of the input signals of following stages. Such a combination of cascode voltage switches has been described by Krambeck et al. in a technical article entitled "High-Speed Compact Circuits with CMOS", appearing in IEEE Journal of Solid-State Circuits, Vol. SC-17, number 3, June 1982 at pages 614-619.
An example of a transistor tree in the logic 18 is presented in FIG. 2 and consists of three types of transistor groups 20, 22 and 24. The internal structures of the logic blocks 18, 40 and 42 (FIG. 4) are by way of example only and other structures are, of course, possible. Each transistor group is, in actuality, of the same form as shown in FIG. 3 for transistor group 20. The transistor group 20 consist of two NMOS FETs 26 and 28 with their sources commonly connected to a source terminal 30 but having separate drain terminals 32 and 34. The gate electrodes 36 and 38 of the transistors 26 and 28 respectively are controlled by complementary input signals V.sub.1 and V.sub.1. Because of the complementary nature of the input signals, only one of the transistors 26 or 28 is conducting at any time. That is, depending upon the value of the input signal V.sub.1, either the drain terminal 32 or the drain terminal 3 has a high conductivity path through the transistor group 20 to the source terminal 30.
Based upon this understanding of the internal operations of the transistor groups 20, 22 and 24, they are arranged and interconnected in the logic 18 so as to provide only a single conduction path from either of the output lines 14 or 16 to ground. That is, only output line 14 or only output line 16 is grounded. In a rigorous DCVS design, such as that illustrated in FIG. 2, this condition can be obtained by connecting each of the drain terminals 32 and 34 to only one source terminal 30 of another transistor group or alternatively to one of the output lines 14 or 16 and by connecting each source terminal 30 to only one drain terminal 32 or 34 or alternatively to ground. However, it is common practice to violate a strict tree structure as long as the condition of a single conductivity path is not violated for any combination of input signals.
Although the DCVS circuit of FIGS. 1 and 2 provides many advantages, there is room for improvement. The loads 10 and 12 take up a larger percentage of chip area when the associated logic block 18 is relatively simple. Only a single logic function has been represented in FIG. 2. It is fairly typical in the design of DCVS to rely upon fairly simple logic blocks 18 but to include several of them within the complete circuit. Significant portions of different logic blocks 18 may be similar but as long as each one has some difference, it is necessary to replicate both the loads as well as the repeating transistor groups. Obviously, this replication requires valuable chip area.